This invention relates to a semiconductor integrated circuit device, and more particularly to an LSTTL (Low Power Schottky Transistor - Transistor Logic) output circuit with inreased breakdown voltage when the potential at the output terminal is high.
FIG. 1 shows a conventional LSTTL output circuit. In FIG. 1, an input signal is applied to the cathode of an SBD (Schottky Barrier Diode) 1. The anode of the SBD is connected through a resistor 2 to a high potential source 3. A first transistor 4 comprises an SBD npn transistor (Schottky clamped npn Transistor). The base of the first transistor is connected to the anode of the SBD, and the collector of the first transistor is connected through a resistor 5 to the thigh potential source 3. A second transistor 6 comprises an SBD npn transistor connected between an output terminal 7 and a low potential source 8, which is grounded. The base of the second transistor is connected to the emitter of the first transistor. A third transistor 9 also comprises an SBD npn transistor. The collector of the third transistor is connected through a resistor 10 to the high potential source 3, the emitter is connected through a resistor 11 to the potential source 8, and the base is connected to the collector of the first transistor. A fourth transistor 12 comprises an npn transistor connected between the collector of the third transistor 9 and the output terminal 7. The base of the fourth transistor is connected to the emitter of the third transistor.
A Darlington circuit comprising the third and fourth transistors 9 and 12 applies a current from the high potential source 3 to the output terminal 7 when the potential at the output terminal 7 is high. The resistor 11 drains the current at the base of the fourth transistor.
A fifth transistor 13 comprises an SBD npn transistor. The base of the fifth transistor 15 is connected through a resistor 14 to the emitter of the first transistor 4, the collector is connected through a resistor 15 to the base of the second transistor 6, and the emitter is connected to the low potential source 8. The fifth transistor 15 discharges the charge at the base of the second transistor 6.
In operation, a low level input signal is applied to the cathode of the SBD 1. At this time, current flows from the high potential source 3 to the resistor 2 and the SBD 1, so that the potential at the base of the first transistor 4 is lower than the sum of the base-emitter voltage V.sub.BE4 of the first transistor 4 and the base-emitter voltage V.sub.BE6 of the second transistor 6. As a result, the first and second transistors are non-conductive. On the other hand, the third transistor 9 is conductive and the current I.sub.H11 flowing through the resistor 11 is expressed by the following formula (A). EQU I.sub.H11 ={V.sub.CC -V.sub.BE9 }/R.sub.11 (A)
where V.sub.CC is the voltage of the potential source, V.sub.BE9 is the base-emitter voltage of the third transistor 9, and R.sub.11 is the resistance of the resistor 11. The third transistor 9 being conductive, the potential at the base of the fourth transistor 12 becomes sufficient to render the fourth transistor conductive. The second transistor 6 being non-conductive and the fourth transistor 12 being conductive, a high level potential develops at the output terminal 7.
When a high level input signal is applied to the cathode of the SBD 1, potential at the base of the first transistor 4 becomes higher than the sum of the base-emitter voltage V.sub.BE4 of the first transistor 4 and the base-emitter voltage V.sub.BE6 of the second transistor 6 so that the first and second transistors 4 and 6 become conductive. The third transistor 9 also is conductive and the current I.sub.L11 flowing through the resistor 11 is expressed by the following formula (B). EQU I.sub.L11 ={V.sub.sat4 +V.sub.BE6 -V.sub.BE9 }/R.sub.11 (B)
where V.sub.sat4 is the collector-base saturation voltage at the first transistor 4, and V.sub.BE6 is the base-emitter voltage at the second transistor 6.
The fourth transistor 12 is non-conductive, because the current I.sub.L11 flowing in the resistor 11 is very small and the potential at the base of the fourth transistor 12 is lower than the base-emitter voltage of the fourth transistor 12. As a result, the second transistor 6 becomes conductive and the fourth transistor 12 becomes non-conductive, so that the voltage at the output terminal 7 is low.
In general, the breakdown voltage BV.sub.ECR of an npn transistor is about 6 V and the breakdown voltage BV.sub.CEO of an SBD npn transistor is about 10 V, so that, in the prior art circuit, the breakdown voltage of the output circuit is determined by the breakdown voltage BV.sub.ECR of the fourth transistor 12 when the output at the output terminal 7 is high. Further, the breakdown voltage BV.sub.ECR of the fourth transistor 12 depends upon the value of the resistor and is higher when the value of the resistor is small. (The breakdown voltage BV.sub.ECR is calculated when the emitter of a transistor has a voltage applied thereto, and the resistor 11 is connected between the base and the standard voltage.)
On the other hand, when the voltage at the output terminal is high, part of the current consumption I.sub.H11 flows from the high potential source 3 through the resistor 10, the base-emitter of the third transistor 9 and the resistor 11 to the low potential source 8. Accordingly, the current consumption depends upon the value of the resistor 11 and increases for a smaller vCalue of the resistor, as is obvious from the above formula (A).
As a result, the prior art device has the following disadvantages. When the output terminal voltage is high, the current consumption I.sub.H11 increases if the value of the resistor 11 is decreased in order to raise the breakdown voltage of the output circuit, while the breakdown voltage becomes low if the value of the resistor 11 is made larger for lowering the current I.sub.H11.